//======================================================================
//    We will gone,the word kept  
//======================================================================
`timescale 1ns/1ps
//=====v1.0====2021.11.10
// tm_apbwr.wr(pwrite,pwaddr,pwdata)
module tm_apbwr
    (
	input				sys_rst								,
	input				sys_clk								,
	// APB
    output  reg[31:0]       APB_paddr                           , //(i)
    output  reg             APB_penable                         , //(i)
    input	  [31:0]	    APB_prdata                          , //(o)
    input	                APB_pready                          , //(o)
    output	reg             APB_psel                            , //(i)
    input	                APB_pslverr                         , //(o)
    output  reg[31:0]       APB_pwdata                          , //(i)
    output	reg             APB_pwrite                           //(i)
    );
	always @(sys_rst) begin
		if (sys_rst) begin
			APB_paddr   <= 0;
			APB_penable <= 0;
			APB_psel    <= 0;
			APB_pwdata  <= 0;
			APB_pwrite  <= 0;
		end
    end
    
    
    task wr(input pwrite, input bit[31:0] pwaddr, input bit[31:0] pwdata);
		@(posedge sys_clk);
            APB_paddr   <= pwaddr; //(i)
            APB_penable <= 0; //(i)
            APB_psel    <= 1; //(i)
            APB_pwdata  <= pwdata; //(i)
            APB_pwrite  <= pwrite; //(i)
		@(posedge sys_clk);
            APB_paddr   <= pwaddr; //(i)
            APB_penable <= 1; //(i)
            APB_psel    <= 1; //(i)
            APB_pwdata  <= pwdata; //(i)
            APB_pwrite  <= pwrite; //(i)
    
        if (APB_pready == 1'b0) begin
            wait (APB_pready == 1'b1);
        end
        
        @(posedge sys_clk);
        APB_paddr   <= 0;
        APB_penable <= 0;
        APB_psel    <= 0;
        APB_pwdata  <= 0;
        APB_pwrite  <= 0;
        
    endtask
    
endmodule 